The invention is generally related to the field of semiconductor device fabrication and more specifically to a method for forming high performance CMOS transistors using a disposable spacer process.
CMOS transistors are currently fabricated using a spacer process. The spacer is used during the formation of the drain extension regions and the source and drain regions. For very short channel length transistors, the drain extension region is necessary to reduce channel hot carrier injection. Channel hot carrier injection into the gate of the transistor during operation reduces the lifetime of the device. In a typical spacer process, the transistor gate is formed by etching a blanket polycrystalline silicon film. The drain extension region is then formed by implanting the required dopant species into the silicon substrate adjacent to the gate. The drain extension region is therefore self aligned to the gate structure. Spacer structures are then formed adjacent to the gate usually with a blanket deposition of silicon nitride followed by an anisotropic nitride etch. This etch leaves nitride spacers on each side of the gate structure. In some instances, these spacer structures are referred to as sidewall spacers. Following the formation of these silicon nitride spacer structures, the source and drain regions are formed by implanting the required dopant species into the silicon substrate adjacent to the sidewall spacer. The spacer performs the function of offsetting the source and drain regions from the edge of the gate i.e., the source and drain regions are aligned to the edges of the spacers. The implanted transistor is then annealed to activate the implanted dopant species. This high temperature anneal process will cause the implanted dopants to diffuse into the silicon substrate resulting in relatively deep drain extension regions and source drain regions.
High performance short channel length CMOS transistors require shallow junctions (i.e., drain extension regions and source drain regions) and low capacitance. Capacitance present in the MOS transistor will introduce RC delays degrading performance. Shallow junctions reduce hot carrier injection and minimize short channel effects such as transistor threshold voltage roll-off. One way in which shallower junctions are achieved is to use a disposable spacer process. In this process, the sidewall spacer is formed followed by the source drain region implantation and anneals processes. The spacer is then removed and the drain extension region formed. The advantage of this method is that the drain extension region will not be annealed with the high temperature source drain process thereby minimizing the diffusion of this region. The MOS transistor is more sensitive to the depth of the drain extension region compared to the depth of the source drain region. While resulting in a shallow drain extension region, the above disposable spacer method does not reduce the capacitance present in the transistor. There is therefore a need for a method that produces both shallow junctions and low capacitance for improved MOS transistor performance.
The instant invention is a method of forming a MOS transistor using novel spacer technology. The invention results in MOS transistors with low capacitance and therefore improved performance compared to the prior art. In an embodiment of the instant invention, the method comprises: providing a semiconductor substrate with an upper surface; forming a gate dielectric on said semiconductor substrate; forming a gate structure on said gate dielectric with a plurality of side surfaces and a top surface; forming a first insulator film of a first thickness on said plurality of side surfaces, said top surface, and said upper surface of said substrate; forming a plurality of sidewall structures against said first insulator film on said plurality of side surfaces wherein said sidewall structure covers a portion of said first insulator film over said upper surface of said substrate; forming a LOCOS type insulator film of a second thickness on said upper surface of said semiconductor substrate wherein said second thickness is greater than said first thickness and said LOCOS type insulator film is formed by thermal oxidation of said first insulator film. This embodiment further comprises: forming a source drain region beneath said LOCOS type insulator film by implanting a first dopant species; removing said plurality of sidewall structures; and forming a drain extension region and a pocket region by implanting said first dopant species and a second dopant species respectively.
In another embodiment of the invention, the method comprises: providing a semiconductor substrate with an upper surface; forming a gate dielectric on said semiconductor substrate; forming a gate structure of a first height on said gate dielectric with a plurality of side surfaces and a top surface; forming a first insulator film of a first thickness on said plurality of side surfaces, said top surface, and said upper surface of said substrate; forming a plurality of sidewall structures with a second height against said first insulator film on said plurality of side surfaces wherein said sidewall structure covers a portion of said first insulator film over said upper surface of said substrate and wherein said second height is less than said first height; forming a LOCOS type insulator film of a second thickness on said upper surface of said semiconductor substrate wherein said second thickness is greater than said first thickness and said LOCOS type insulator film is formed by thermal oxidation of said first insulator film; and forming a spacer structure on said top surface of said gate structure and on said plurality of side surfaces of said gate structure above said sidewall structure of a second height wherein said spacer structure is formed by thermal oxidation of said first insulator film. The method further comprises: forming a source drain region beneath said LOCOS type insulator film by implanting a first dopant species; removing said plurality of sidewall structures; and forming a drain extension region and a pocket region by implanting said first dopant species and a second dopant species respectively.